There are many electrical and semiconductor devices and processes which can be improved by a technique for more rapid silicon compound or glass etch. The test of a good etch process is its ability to make high aspect ratio holes. In the prior art, the highest reported ratio of depth/diameter, i.e., aspect ratio, R, of such holes in silicon compounds is on the order of R=1.5. Also, as the diameter of the holes has become smaller, the achievable aspect ratios employing dry etch technology has been getting worse. Accordingly, there is a need for improved processes for silicon based materials. It is understood that any etch process which can quickly make high aspect ratio holes in a material without surface damage is a good general etchant of the material.
Ion bombardment of surfaces is an important aspect of plasma etching, reactive ion etching, and sputter deposition. Ion bombardment also is an important part of several analytical techniques such as secondary ion mass spectrometry (SIMS) and low energy ion scattering spectroscopy (LEIS). Auger electron spectrometry (AES) also employs low energy inert gas ions for physical sputtering to obtain erosion to support depth profiling. Although these have become very important processes, the ion induced surface chemistry and alteration of new surface chemical, physical and electronic characteristics are very complex and remain poorly understood processes. This has lead to the empirical development of most commercial plasma assisted etching processes.
Plasmas are partially ionized quasi-neutral gases. They can be created in a vacuum chamber by applying enough electric field to ionize the gases. The power source may be a DC electric field, inductive RF coil, microwaves or a capacitively coupled RF electric field. Electrons have small mass relative to other particles so most of the energy gained in these systems is initially absorbed by the electrons. These high energy electrons collide with other particles and ionize the gas and sustain the plasma. The typical ionization potential is high so that the majority of molecules and atoms stay neutral. Eventually, a DC potential will build up between a plasma and any dielectric surface nearby, preventing any further imbalance.
In general, semiconductor processing plasmas are in a state of thermal non-equilibrium and are affected by the following:
(a) Power--By increasing power absorbed the sheath potential is increased as well as the number of ions produced. Any wafer within the plasma will experience induced temperature increases from increased ion energy bombardment as well as increased ion flux. Obviously, more damage can be done to the substrate at higher powers. PA1 (b) Pressure--At higher pressures, more gas molecules are available which is generally believed to result in higher ion flux. Very fast etching is frequently accompanied by surface damage usually occurring with energetic ions. While such surface damage is expected with heavy ions, it has also been documented with light ions. PA1 (c) Device Configuration--Parameters such as chamber geometry including positioning of the substrate, magnet configuration, chamber materials and ion density uniformity will affect the etching process.
It is postulated that the explanation for the distinctly different etching rates of materials by various etchant gases has to do with the ability of the reactive gas molecule to penetrate into the stirface being etched and to break the subsurface bond or lower the binding energy for the surface atoms and to replace that bond by bonding itself to the subsurface such that the released product is volatile at the temperature of release. It is believed that when an energetic ion strikes a solid, it transfers its energy to near surface atoms through a series of elastic collisions and electronic and vibrational processes. Collisional cascade effects can produce ion implantation, crystalline damage, ion mixing and physical sputtering. These effects can also result from low energy ion bombardment. Ion mixing is the process under which target atoms are relocated by ion impact, which process is broken up by recoil and cascade contributions. It is believed that mixing processes may be important in enhancing volatile product formation. This is distinct from sputtering in which near surface atoms receive enough momentum transfer perpendicular to the surface to overcome the surface potential barrier and thereby escape into the vacuum.
There are currently several types of equipment being most frequently used for plasma etching. Confined plasma reactors are one type of such apparatus which employ generally closely spaced parallel plates which are excited by an RF power source to induce and sustain the plasma therebetween. These relatively simple essentially parallel plate electrodes devices have the difficulty that the plasma density and ion energy cannot be separately controlled and accordingly high ion energies cannot be curtailed in high power requirement situations.
Typically, in the prior art, these reactors consist of a pair of closely separated nearly planar electrodes characterized by pressure on the order of 0.3-0.5 Torr operation for etch. This pressure generally gives them isotropic etch characteristics. Previously,, these reactors have been too slow for commercial etch use in a single wafer operation.
A major application for high aspect ratio holes is in the manufacture of semiconductor devices in the creation of contact holes, i.e., "VIAS" These VIAS are tiny holes made through a dielectric layer on the surface of an integrated circuit to permit electrical connection to the surface of the circuit or for connection to the metal interconnect strips which had been previously laid down on the dielectric layer overlaying the active elements of the circuit. However, such an etching process is not limited to integrated circuits since there are many devices and objects made from SiO.sub.x, or glass which can be improved by an improved micromachinery process which can produce high aspect ratio holes in such materials.
The role of nitrogen in RIE of a SiO.sub.2 has been reported, Smolinsky, J. Electro Chemistry, Vol. 129, No. 5, May 1982, pp. 1036-1040. This report indicated an improved aspect ratio blot did not overcome the problem of punch through as subsequently described.
Our inventive process will be explained in connection with some special problems in semiconductor integrated circuit manufacture, but it is understood that the applications of our process is not so limited.
Semiconductor integrated circuits require many low resistance connections between portions of the circuit. These are called interconnects. Interconnects are usually metal but can also be made from doped polysilicon. Several levels of interconnects separated by dielectric layers are usually required. Typically, the metal employed for the interconnects is Al or contains Al because it has low resistance and is relatively inexpensive to apply.
It is also necessary to provide connections between the different levels of interconnects. Broadly described, this is accomplished by opening a hole from the surface down through the dielectric layer at the selected location until the underlying interconnect is reached. Next, the hole or "VIA" is filled with low resistivity material, usually metal, down to the top of the dielectric and then the upper surface is coated with Al. Next, a thin coating of an antireflective coating (ARC), usually of titanium nitride, TiN, is applied over the metal layer. Next a resist is layered over the ARC layer and optically exposed with UV radiation to form a mask pattern. The patterned mask is used to control the etch of the metal to form the next level of interconnect. The ARC coating reduces optical reflections from the metal and enables a sharper focus on the mask of the optical images to be formed. A next layer of protective dielectric is applied over the interconnects.
In such multilayer structures, it is necessary to apply planarization processes to the surface of each dielectric layer to smooth the final surface of each layer so that metal does not have to cover sharp underlying edges and so that the photographic processes for the next layer will have a single flat depth of field for sharper focus. This planarization requirement has lead to a new problem. As a result of the large global planarization processes, as seen in FIG. 1, the distance from the planarized surface I to the underlying contacting surface across a single chip can now widely vary, i.e, 5500.ANG. to 16500.ANG.. The etch process for the VIAS must therefore be able to make the deeper holes 2' while at the same time not damaging the materials at the bottom of the shallow holes 2.
With conventional prior etch processes, in those instances where the VIA hole depths vary widely across the chip, the exposed ARC layer 8 at the bottom of the shallow VIAS 2 is frequently etched away even when the normal 350.ANG. TiN ARC layer is thickened substantially to 1000.ANG.. This results in sputtering of the underlying metal 7 and/or damage to the underlying surface 9. Also, in the prior processes, a polymer build up 10 usually occurs in the VIAS holes which is difficult to remove. Also, this often results in the resistance of the resultant VIAS being substantially higher.